1. Field of the Invention
The present invention relates to an A/D converter and more particularly, to an A/D converter in which the function of multiplying an analogue input by a digital input is incorporated in advance into an encoder portion for A/D conversion for use in an environment in which such multiplication is required.
2. Description of the Prior Art
Recently, digital integrated circuit techniques have been significantly developed. Thus, even in the field in which various signals were conventionally processed using an analog circuit, such signals have been processed in a digital manner for high performance, high integration and high function. More specifically, when signals which are originally analog, such as an audio signal and an video signal are processed in a digital manner, an A/D converter is required.
FIG. 1 is a circuit diagram showing an example of an A/D converter of a serial-parallel comparison type as one example of such a conventional A/D converter, which is disclosed in, for example, Japanese Patent Laying-Open Gazette No. 131123/1982.
A serial-parallel A/D converter shown in FIG. 1 comprises an input terminal 21 receiving an analogue signal, a first A/D converting portion A of a parallel comparison type and a second A/D converting portion B of a parallel comparison type. More specifically, the first A/D converting portion A of a parallel comparison type comprises voltage comparators 22, 23 and 24 receiving three kinds of reference voltages V.sub.1, V.sub.2 and V.sub.3 as respective inputs obtained by dividing a constant voltage V.sub.R by ladder resistors R.sub.1 to R.sub.16, a determining circuit 25 receiving outputs of the voltage comparators, and an encoder 26 receiving outputs of the determining circuit 25. The encoder 26 has digital output terminals 27a and 27b. In addition, the second A/D converting portion B of a parallel comparison type comprises switches S.sub.1 to S.sub.12 connected to reference voltages v.sub.1 to v.sub.12 applied by the ladder resistors R.sub.1 to R.sub.16, respectively, the switches being divided into a first group C.sub.1 of switches, a second group C.sub.2 of switches, a third group C.sub.3 of switches and a fourth group C.sub.4 of switches. Opening or closing of the switches in respective groups is controlled by control signals from the determining circuit 25. The second A/D converting portion B of a parallel comparison type further comprises voltage comparators 28, 29 and 30 receiving reference voltages as respective one inputs obtained through the group of switches selected by the control signal, a determining circuit 31 receiving outputs of the voltage comparators, and an encoder 32 receiving outputs of the determining circuit 31. The encoder 32 has digital output terminals 33a and 33b.
Description is now made on operation of the conventional A/D converter of a serial-parallel comparison type shown in FIG. 1.
When an analogue input signal V.sub.X is applied to the input terminal 21, the signal is applied to the respective input terminals of the voltage comparators 22, 23 and 24 in common. On the other hand, the reference voltages V.sub.1, V.sub.2 and V.sub.3 generated by dividing a constant voltage V.sub.R by the ladder resistors R.sub.1 to R.sub.16 are applied to the other input terminals of the voltage comparators 22, 23 and 24, respectively. Each of the voltage comparators compares the applied analogue input signal with the reference voltage. If the analog input signal is larger, the voltage comparator outputs a signal at an "H" level. For example, when the analog input signal V.sub.X is in the range of V.sub.2 &lt;V.sub.X &lt;V.sub.1, the output of the voltage comparator 22 is at an "L" level and the outputs of the voltage comparators 23 and 24 are at the "H" level.
The determining circuit 25 receives the outputs of the voltage comparators 22, 23 and 24 determines that the analogue input signal V.sub.X is a value within the range of V.sub.2 &lt;V.sub.X &lt;V.sub.1 and applies a signal representing the determined results to the encoder 26. Correspondingly, the encoder 26 outputs a digital signal of more significant digits corresponding to the analogue input signal V.sub.X through the output terminal 27a and 27b. Consequently, a first A/D converting operation is completed.
The determining circuit 25 applies a control signal for closing each of the switches S.sub.1 to S.sub.3 in the group C.sub.1 of switches when it determines that the analog input signal V.sub.X is larger than the reference voltage V.sub.1, a control signal for closing each of the switches S.sub.4 to S.sub.6 in the group C.sub.2 of switches when it determines that V.sub.X is between V.sub.1 and V.sub.2, a control signal for closing each of the switches S.sub.7 to S.sub.9 in the group C.sub.3 of switches when it determines that V.sub.X is between V.sub.2 and V.sub.3, and a control signal for closing each of the switches S.sub.10 to S.sub.12 in the group C.sub.4 of switches when it determines that V.sub.X is smaller than V.sub.3.
For example, if and when the determining circuit 25 determines that V.sub.X is between V.sub.1 and V.sub.2 as described above, the switches S.sub.4 to S.sub.6 in the group C.sub.2 of switches are closed. As a result, the reference voltages .upsilon..sub.4, .upsilon..sub.5 and .upsilon..sub.6 are applied to the respective one input terminals of the voltage comparators 28, 29 and 30. The analogue input signal V.sub.X is applied to the respective other input terminals of the voltage comparators 28, 29 and 30 through the input terminal 21 in common. Each of the voltage comparators compares the applied analogue inpu signal with the reference voltage. If the analogue input signal is larger, the comparator outputs a signal at the "H" level. The determining circuit 31 receives the outputs of the voltage comparators 28, 29 and 30 and determines whether the analogue input signal V.sub.X takes a value between V.sub.1 and .upsilon..sub.4, a value between .upsilon..sub.4 and .upsilon..sub.5, a value between .upsilon..sub.5 and .upsilon..sub.6 or a value between .upsilon..sub.6 and V.sub.2. The encoder 32 is responsive to the determination output for outputting a digital signal of less significant digits corresponding to the input analogue signal V.sub.X through the output terminals 33a and 33b.
Thus, the A/D converter of a serial-parallel comparison type shown in FIG. 1 is adapted such that it is determined that the analogue signal V.sub.X exists, for example, between the reference voltages V.sub.1 and V.sub.2 so that a digital code of more significant digits is obtained, by the first A/D converting portion A of a parallel comparison type, and a digital code of less significant digits is obtained to achieve higher resolution, by the second A/D converting portion B of a parallel comparison type.
Meanwhile, in a digital integrated circuit such as a digital filter, it is necessary that an analog input is converted into digital data and then, the digital data is multiplied by another digital input. In such a case, an output of an A/D converter has been conventionally applied to a multiplier in another chip. Hoever, such a structure presents difficulty in providing high integration. A circuit having both functions of an A/D converter and a multiplier on a single chip, which is described in, for example, U.S. Pat. application No. 111,047, filed Oct. 21, 1987.
FIG. 2 is a circuit diagram showing an example of such a semiconductor integrated circuit, which is adapted such that the encoder portion (for example, corresponding to the encoder 26 or 32 shown in FIG. 1) of an A/D converter of a parallel comparison type has a function of multiplying an output of a determining circuit (for example, corresponding to the determining circuit 25 or 31 shown in FIG. 1) by another digital input and outputting the result.
Referring to FIG. 2, a constant voltage is supplied through an input terminal 41, the constant voltage being divided by ladder resistors 42 to 45 so that reference voltages Va, Vb and Vc are obtained. The reference voltages Va, Vb and Vc are applied to respective one input terminals of voltage comparators 46, 47 and 48. At the same time an analog inpu signal V.sub.X inputted through an input terminal 49 is applied to the respective other inputs of the voltage comparators 46, 47 and 48 in common. Each of the voltage comparators compares the applied analogue input signal with the reference signal and outputs a signal at an "H" level when the analogue input signal is larger. A determining circuit 50 receives outputs of the voltage comparators 46, 47 and 48 and determines whether the analogue input signal V.sub.X takes a value larger than Va, a value between Va and Vb, a value between Vb and Vc or a value smaller than Vc. Output signals A.sub.3, A.sub.2, A.sub.1 and A.sub.0 of the determining circuit 50 are applied to a control circuit 51 having a multiplying function corresponding to the encoder portion of the A/D converter. A control signal generating circuit 54 is responsive to other digital input signals R.sub.1 and R.sub.0 applied to input terminals 52 and 53 for generating control signals and applying the same to the control circuit 51. The control circuit 51 comprises a plurality of transfer gates 55 to 62 and a plurality of OR gates 63 to 65. The results of multiplying the analogue input signal V.sub.X by the digital input signals R.sub.1 and R.sub.0 are outputted from the control circuit 51 as digital signals X.sub.3, X.sub.2, X.sub.1 and X.sub.0.
Operation of the circuit shown in FIG. 2 is now described. Briefly stated, description is made on a case in which the analog input signal applied through the input terminal 49 takes a value "2" and the digital data applied through the input terminals 52 and 53 takes a value "3".
When the analog input signal V.sub.X is applied to the input terminal 49, the signal V.sub.X is applied to respective one input terminals of the voltage comparators 46, 47 and 48 in common. The reference voltages Va, Vb and Vc generated by dividing a voltage by the ladder resistors 42 to 45 are applied to their other input terminals of the voltage comparators 46, 47 and 48, respectively. In this case, since the analog input signal which takes a value "2", which is a value between Va and Vb. Thus, the output of the voltage comparator 46 attains the "L" level and the outputs of the voltage comparators 47 and 48 attain the "H" level.
The determining circuit 50 receives the outputs of the voltage comparators 46, 47 and 48, determines that the analogue input signal V.sub.X takes a value in the range of Vb&lt;V.sub.X &lt;Va, and applies signals representing the determined result to the control circuit 51. More specifically, the determining circuit 50 determines the output levels of the voltage comparators 46, 47 and 48 arranged in parallel, and provides an output indicating a voltage comparator corresponding to a most significant digit, of voltage comparators which generate "1" (a high level) thereamong. For example, when the analogue input signal V.sub.X takes a value "2.infin., the outputs of the voltage comparators 46, 47 and 48 are "0", "1" and ;b "1", the output "1" of a most significant digit thereof being applied by the voltage comparator 47. Thus, only the signal A.sub.2 corresponding to the voltage comparator 47, of the outputs A.sub.3, A.sub.2, A.sub.1 and A.sub.0 of the determining circuit 50 is "1" and all of the other signals A.sub.3, A.sub.1 and A.sub.0 are "0". In addition, when the analog input signal V.sub.X is less than V.sub.C, for example, all of the outputs of the voltage comparators 46, 47 and 48 are "0" (a low level). In this case, only the output A.sub.0 of the determining circuit 50 is "1" and all of the other outputs A.sub.3, A.sub.2 and A.sub.1 are "0".
The control signal generating circuit 54 receives the digital input signals R.sub.1 and R.sub.0, generates five kinds of control signals R.sub.0, R.sub.1 +R.sub.0, R.sub.1, R.sub.1 R.sub.0 and R.sub.1 R.sub.0 and supplies the same as gate signals of the transfer gates constituting the control circuit 51. When the digital input data takes a value "3" as described above, both R.sub.1 and R.sub.0 are "1". Thus, the above described five kinds of control signals are "1", .intg.0", "1", "0" and "1" in this order. Consequently, the transfer gates 55, 57, 59, 60, 61 and 62 are turned on and the transfer gates 56 and 58 are turned off. Thus, when the analog input signal takes a value "2", that is, A.sub.3 equals 0, A.sub.2 equals 1, A.sub.1 equals 0 and A.sub.0 equals 10, the outputs X.sub.3, X.sub.2, X.sub.1 and X.sub.0 of the control circuit 51 X.sub.3 equals 0, 1, 1 and 0, respectively, which indicates a value "6". More specifically, the value "6" indicates "2.times.3" corresponding to the result of multiplying the value "2" of the analogue input signal by the value "3" of the digital input data.
However, in the above described semiconductor integrated circuit, the structures of the above described control signal generating portion and the control circuit are both complicated and the area of the circuit is significantly increased if the number of input bits is increased.